/* SPDX-License-Identifier: GPL-2.0 */


#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H



#define TEGRA234_CLK_ACTMON			1U

#define TEGRA234_CLK_ADSP			2U

#define TEGRA234_CLK_ADSPNEON			3U

#define TEGRA234_CLK_AHUB			4U

#define TEGRA234_CLK_APB2APE			5U

#define TEGRA234_CLK_APE			6U

#define TEGRA234_CLK_AUD_MCLK			7U

#define TEGRA234_CLK_AXI_CBB			8U

#define TEGRA234_CLK_CAN1			9U

#define TEGRA234_CLK_CAN1_HOST			10U

#define TEGRA234_CLK_CAN2			11U

#define TEGRA234_CLK_CAN2_HOST			12U

#define TEGRA234_CLK_CLK_M			14U

#define TEGRA234_CLK_DMIC1			15U

#define TEGRA234_CLK_DMIC2			16U

#define TEGRA234_CLK_DMIC3			17U

#define TEGRA234_CLK_DMIC4			18U

#define TEGRA234_CLK_DPAUX			19U

#define TEGRA234_CLK_NVJPG1			20U

#define TEGRA234_CLK_ACLK			21U

#define TEGRA234_CLK_MSS_ENCRYPT		22U

#define TEGRA234_CLK_EQOS_RX_INPUT		23U

#define TEGRA234_CLK_AON_APB			25U

#define TEGRA234_CLK_AON_NIC			26U

#define TEGRA234_CLK_AON_CPU_NIC		27U

#define TEGRA234_CLK_PLLA1			28U

#define TEGRA234_CLK_DSPK1			29U

#define TEGRA234_CLK_DSPK2			30U

#define TEGRA234_CLK_EMC			31U

#define TEGRA234_CLK_EQOS_AXI			32U

#define TEGRA234_CLK_EQOS_PTP_REF		33U

#define TEGRA234_CLK_EQOS_RX			34U

#define TEGRA234_CLK_EQOS_TX			35U

#define TEGRA234_CLK_EXTPERIPH1			36U

#define TEGRA234_CLK_EXTPERIPH2			37U

#define TEGRA234_CLK_EXTPERIPH3			38U

#define TEGRA234_CLK_EXTPERIPH4			39U

#define TEGRA234_CLK_FUSE			40U

#define TEGRA234_CLK_GPC0CLK			41U

#define TEGRA234_CLK_GPU_PWR			42U


#define TEGRA234_CLK_HOST1X			46U

#define TEGRA234_CLK_XUSB_HS_HSICP		47U

#define TEGRA234_CLK_I2C1			48U

#define TEGRA234_CLK_I2C2			49U

#define TEGRA234_CLK_I2C3			50U

#define TEGRA234_CLK_I2C4			51U

#define TEGRA234_CLK_I2C6			52U

#define TEGRA234_CLK_I2C7			53U

#define TEGRA234_CLK_I2C8			54U

#define TEGRA234_CLK_I2C9			55U

#define TEGRA234_CLK_I2S1			56U

#define TEGRA234_CLK_I2S1_SYNC_INPUT		57U

#define TEGRA234_CLK_I2S2			58U

#define TEGRA234_CLK_I2S2_SYNC_INPUT		59U

#define TEGRA234_CLK_I2S3			60U

#define TEGRA234_CLK_I2S3_SYNC_INPUT		61U

#define TEGRA234_CLK_I2S4			62U

#define TEGRA234_CLK_I2S4_SYNC_INPUT		63U

#define TEGRA234_CLK_I2S5			64U

#define TEGRA234_CLK_I2S5_SYNC_INPUT		65U

#define TEGRA234_CLK_I2S6			66U

#define TEGRA234_CLK_I2S6_SYNC_INPUT		67U

#define TEGRA234_CLK_ISP			69U

#define TEGRA234_CLK_EQOS_RX_M			70U

#define TEGRA234_CLK_MAUD			71U

#define TEGRA234_CLK_MIPI_CAL			72U

#define TEGRA234_CLK_MPHY_CORE_PLL_FIXED	73U

#define TEGRA234_CLK_MPHY_L0_RX_ANA		74U

#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT		75U

#define TEGRA234_CLK_MPHY_L0_RX_SYMB		76U

#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT	77U

#define TEGRA234_CLK_MPHY_L0_TX_SYMB		78U

#define TEGRA234_CLK_MPHY_L1_RX_ANA		79U

#define TEGRA234_CLK_MPHY_TX_1MHZ_REF		80U

#define TEGRA234_CLK_NVCSI			81U

#define TEGRA234_CLK_NVCSILP			82U

#define TEGRA234_CLK_NVDEC			83U

#define TEGRA234_CLK_HUB			84U

#define TEGRA234_CLK_DISP			85U

#define TEGRA234_CLK_NVDISPLAY_P0		86U

#define TEGRA234_CLK_NVDISPLAY_P1		87U

#define TEGRA234_CLK_DSC			88U

#define TEGRA234_CLK_NVENC			89U

#define TEGRA234_CLK_NVJPG			90U

#define TEGRA234_CLK_OSC			91U

#define TEGRA234_CLK_AON_TOUCH			92U

#define TEGRA234_CLK_PLLA			93U

#define TEGRA234_CLK_PLLAON			94U

#define TEGRA234_CLK_PLLE			100U

#define TEGRA234_CLK_PLLP			101U

#define TEGRA234_CLK_PLLP_OUT0			102U

#define TEGRA234_CLK_UTMIP_PLL			103U

#define TEGRA234_CLK_PLLA_OUT0			104U

#define TEGRA234_CLK_PWM1			105U

#define TEGRA234_CLK_PWM2			106U

#define TEGRA234_CLK_PWM3			107U

#define TEGRA234_CLK_PWM4			108U

#define TEGRA234_CLK_PWM5			109U

#define TEGRA234_CLK_PWM6			110U

#define TEGRA234_CLK_PWM7			111U

#define TEGRA234_CLK_PWM8			112U

#define TEGRA234_CLK_RCE_CPU_NIC		113U

#define TEGRA234_CLK_RCE_NIC			114U

#define TEGRA234_CLK_AON_I2C_SLOW		117U

#define TEGRA234_CLK_SCE_CPU_NIC		118U

#define TEGRA234_CLK_SCE_NIC			119U

#define TEGRA234_CLK_SDMMC1			120U

#define TEGRA234_CLK_UPHY_PLL3			121U

#define TEGRA234_CLK_SDMMC4			123U

#define TEGRA234_CLK_SE				124U

#define TEGRA234_CLK_SOR0_PLL_REF		125U

#define TEGRA234_CLK_SOR0_REF			126U

#define TEGRA234_CLK_SOR1_PLL_REF		127U

#define TEGRA234_CLK_PRE_SOR0_REF		128U

#define TEGRA234_CLK_SOR1_REF			129U

#define TEGRA234_CLK_PRE_SOR1_REF		130U

#define TEGRA234_CLK_SOR_SAFE			131U

#define TEGRA234_CLK_SOR0_DIV			132U

#define TEGRA234_CLK_DMIC5			134U

#define TEGRA234_CLK_SPI1			135U

#define TEGRA234_CLK_SPI2			136U

#define TEGRA234_CLK_SPI3			137U

#define TEGRA234_CLK_I2C_SLOW			138U

#define TEGRA234_CLK_SYNC_DMIC1			139U

#define TEGRA234_CLK_SYNC_DMIC2			140U

#define TEGRA234_CLK_SYNC_DMIC3			141U

#define TEGRA234_CLK_SYNC_DMIC4			142U

#define TEGRA234_CLK_SYNC_DSPK1			143U

#define TEGRA234_CLK_SYNC_DSPK2			144U

#define TEGRA234_CLK_SYNC_I2S1			145U

#define TEGRA234_CLK_SYNC_I2S2			146U

#define TEGRA234_CLK_SYNC_I2S3			147U

#define TEGRA234_CLK_SYNC_I2S4			148U

#define TEGRA234_CLK_SYNC_I2S5			149U

#define TEGRA234_CLK_SYNC_I2S6			150U

#define TEGRA234_CLK_MPHY_FORCE_LS_MODE		151U

#define TEGRA234_CLK_TACH0			152U

#define TEGRA234_CLK_TSEC			153U

#define TEGRA234_CLK_TSEC_PKA			154U

#define TEGRA234_CLK_UARTA			155U

#define TEGRA234_CLK_UARTB			156U

#define TEGRA234_CLK_UARTC			157U

#define TEGRA234_CLK_UARTD			158U

#define TEGRA234_CLK_UARTE			159U

#define TEGRA234_CLK_UARTF			160U

#define TEGRA234_CLK_PEX1_C6_CORE		161U

#define TEGRA234_CLK_UART_FST_MIPI_CAL		162U

#define TEGRA234_CLK_UFSDEV_REF			163U

#define TEGRA234_CLK_UFSHC			164U

#define TEGRA234_CLK_USB2_TRK			165U

#define TEGRA234_CLK_VI				166U

#define TEGRA234_CLK_VIC			167U

#define TEGRA234_CLK_CSITE			168U

#define TEGRA234_CLK_IST			169U

#define TEGRA234_CLK_JTAG_INTFC_PRE_CG		170U

#define TEGRA234_CLK_PEX2_C7_CORE		171U

#define TEGRA234_CLK_PEX2_C8_CORE		172U

#define TEGRA234_CLK_PEX2_C9_CORE		173U

#define TEGRA234_CLK_DLA0_FALCON		174U

#define TEGRA234_CLK_DLA0_CORE			175U

#define TEGRA234_CLK_DLA1_FALCON		176U

#define TEGRA234_CLK_DLA1_CORE			177U

#define TEGRA234_CLK_SOR0			178U

#define TEGRA234_CLK_SOR1			179U

#define TEGRA234_CLK_SOR_PAD_INPUT		180U

#define TEGRA234_CLK_PRE_SF0			181U

#define TEGRA234_CLK_SF0			182U

#define TEGRA234_CLK_SF1			183U

#define TEGRA234_CLK_DSI_PAD_INPUT		184U

#define TEGRA234_CLK_PEX2_C10_CORE		187U

#define TEGRA234_CLK_UARTI			188U

#define TEGRA234_CLK_UARTJ			189U

#define TEGRA234_CLK_UARTH			190U

#define TEGRA234_CLK_FUSE_SERIAL		191U

#define TEGRA234_CLK_QSPI0_2X_PM		192U

#define TEGRA234_CLK_QSPI1_2X_PM		193U

#define TEGRA234_CLK_QSPI0_PM			194U

#define TEGRA234_CLK_QSPI1_PM			195U

#define TEGRA234_CLK_VI_CONST			196U

#define TEGRA234_CLK_NAFLL_BPMP			197U

#define TEGRA234_CLK_NAFLL_SCE			198U

#define TEGRA234_CLK_NAFLL_NVDEC		199U

#define TEGRA234_CLK_NAFLL_NVJPG		200U

#define TEGRA234_CLK_NAFLL_TSEC			201U

#define TEGRA234_CLK_NAFLL_VI			203U

#define TEGRA234_CLK_NAFLL_SE			204U

#define TEGRA234_CLK_NAFLL_NVENC		205U

#define TEGRA234_CLK_NAFLL_ISP			206U

#define TEGRA234_CLK_NAFLL_VIC			207U

#define TEGRA234_CLK_NAFLL_AXICBB		209U

#define TEGRA234_CLK_NAFLL_NVJPG1		210U

#define TEGRA234_CLK_NAFLL_PVA0_CORE		211U

#define TEGRA234_CLK_NAFLL_PVA0_VPS		212U

#define TEGRA234_CLK_DBGAPB			213U

#define TEGRA234_CLK_NAFLL_RCE			214U

#define TEGRA234_CLK_LA				215U

#define TEGRA234_CLK_PLLP_OUT_JTAG		216U

#define TEGRA234_CLK_SDMMC4_AXICIF		217U

#define TEGRA234_CLK_SDMMC_LEGACY_TM		219U

#define TEGRA234_CLK_PEX0_C0_CORE		220U

#define TEGRA234_CLK_PEX0_C1_CORE		221U

#define TEGRA234_CLK_PEX0_C2_CORE		222U

#define TEGRA234_CLK_PEX0_C3_CORE		223U

#define TEGRA234_CLK_PEX0_C4_CORE		224U

#define TEGRA234_CLK_PEX1_C5_CORE		225U

#define TEGRA234_CLK_PEX0_C0_CORE_M		229U

#define TEGRA234_CLK_PEX0_C1_CORE_M		230U

#define TEGRA234_CLK_PEX0_C2_CORE_M		231U

#define TEGRA234_CLK_PEX0_C3_CORE_M		232U

#define TEGRA234_CLK_PEX0_C4_CORE_M		233U

#define TEGRA234_CLK_PEX1_C5_CORE_M		234U

#define TEGRA234_CLK_PEX1_C6_CORE_M		235U

#define TEGRA234_CLK_GPC1CLK			236U

#define TEGRA234_CLK_PLLC4			237U

#define TEGRA234_CLK_PLLC4_OUT1			239U

#define TEGRA234_CLK_PLLC4_OUT2			240U

#define TEGRA234_CLK_PLLC4_MUXED		241U

#define TEGRA234_CLK_PLLC4_VCO_DIV2		242U

#define TEGRA234_CLK_PLLNVHS			243U

#define TEGRA234_CLK_PEX2_C7_CORE_M		244U

#define TEGRA234_CLK_PEX2_C8_CORE_M		245U

#define TEGRA234_CLK_PEX2_C9_CORE_M		246U

#define TEGRA234_CLK_PEX2_C10_CORE_M		247U

#define TEGRA234_CLK_MGBE0_RX_INPUT		248U

#define TEGRA234_CLK_MGBE1_RX_INPUT		249U

#define TEGRA234_CLK_MGBE2_RX_INPUT		250U

#define TEGRA234_CLK_MGBE3_RX_INPUT		251U

#define TEGRA234_CLK_PEX_SATA_USB_RX_BYP	254U

#define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT	255U

#define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT	256U

#define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT	257U

#define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT	258U

#define TEGRA234_CLK_NVHS_RX_BYP_REF		263U

#define TEGRA234_CLK_NVHS_PLL0_MGMT		264U

#define TEGRA234_CLK_XUSB_CORE_DEV		265U

#define TEGRA234_CLK_XUSB_CORE_MUX		266U

#define TEGRA234_CLK_XUSB_CORE_HOST		267U

#define TEGRA234_CLK_XUSB_CORE_SS		268U

#define TEGRA234_CLK_XUSB_FALCON		269U

#define TEGRA234_CLK_XUSB_FALCON_HOST		270U

#define TEGRA234_CLK_XUSB_FALCON_SS		271U

#define TEGRA234_CLK_XUSB_FS			272U

#define TEGRA234_CLK_XUSB_FS_HOST		273U

#define TEGRA234_CLK_XUSB_FS_DEV		274U

#define TEGRA234_CLK_XUSB_SS			275U

#define TEGRA234_CLK_XUSB_SS_DEV		276U

#define TEGRA234_CLK_XUSB_SS_SUPERSPEED		277U

#define TEGRA234_CLK_NAFLL_CLUSTER0		280U 
#define TEGRA234_CLK_NAFLL_CLUSTER0_CORE	280U

#define TEGRA234_CLK_NAFLL_CLUSTER1		281U 
#define TEGRA234_CLK_NAFLL_CLUSTER1_CORE	281U

#define TEGRA234_CLK_NAFLL_CLUSTER2		282U 
#define TEGRA234_CLK_NAFLL_CLUSTER2_CORE	282U

#define TEGRA234_CLK_CAN1_CORE			284U

#define TEGRA234_CLK_CAN2_CORE			285U

#define TEGRA234_CLK_PLLA1_OUT1			286U

#define TEGRA234_CLK_PLLNVHS_HPS		287U

#define TEGRA234_CLK_PLLREFE_VCOOUT		288U

#define TEGRA234_CLK_CLK_32K			289U

#define TEGRA234_CLK_UTMIPLL_CLKOUT48		291U

#define TEGRA234_CLK_UTMIPLL_CLKOUT480		292U

#define TEGRA234_CLK_PLLNVCSI			294U

#define TEGRA234_CLK_PVA0_CPU_AXI		295U

#define TEGRA234_CLK_PVA0_VPS			297U

#define TEGRA234_CLK_NAFLL_DLA0_CORE		299U

#define TEGRA234_CLK_NAFLL_DLA0_FALCON		300U

#define TEGRA234_CLK_NAFLL_DLA1_CORE		301U

#define TEGRA234_CLK_NAFLL_DLA1_FALCON		302U

#define TEGRA234_CLK_AON_UART_FST_MIPI_CAL	303U

#define TEGRA234_CLK_GPUSYS			304U

#define TEGRA234_CLK_I2C5			305U

#define TEGRA234_CLK_FR_SE			306U

#define TEGRA234_CLK_BPMP_CPU_NIC		307U

#define TEGRA234_CLK_BPMP_CPU			308U

#define TEGRA234_CLK_TSC			309U

#define TEGRA234_CLK_EMCSA_MPLL			310U

#define TEGRA234_CLK_EMCSB_MPLL			311U

#define TEGRA234_CLK_EMCSC_MPLL			312U

#define TEGRA234_CLK_EMCSD_MPLL			313U

#define TEGRA234_CLK_PLLC			314U

#define TEGRA234_CLK_PLLC2			315U

#define TEGRA234_CLK_TSC_REF			317U

#define TEGRA234_CLK_FUSE_BURN			318U

#define TEGRA234_CLK_PLLGBE			319U

#define TEGRA234_CLK_PLLGBE_HPS			320U

#define TEGRA234_CLK_EMCSA_EMC			321U

#define TEGRA234_CLK_EMCSB_EMC			322U

#define TEGRA234_CLK_EMCSC_EMC			323U

#define TEGRA234_CLK_EMCSD_EMC			324U

#define TEGRA234_CLK_PLLE_HPS			326U

#define TEGRA234_CLK_PLLREFE_VCOOUT_GATED	327U

#define TEGRA234_CLK_PLLP_DIV17			328U

#define TEGRA234_CLK_SOC_THERM			329U

#define TEGRA234_CLK_TSENSE			330U

#define TEGRA234_CLK_FR_SEU1			331U

#define TEGRA234_CLK_NAFLL_OFA			333U

#define TEGRA234_CLK_OFA			334U

#define TEGRA234_CLK_NAFLL_SEU1			335U

#define TEGRA234_CLK_SEU1			336U

#define TEGRA234_CLK_SPI4			337U

#define TEGRA234_CLK_SPI5			338U

#define TEGRA234_CLK_DCE_CPU_NIC		339U

#define TEGRA234_CLK_DCE_NIC			340U

#define TEGRA234_CLK_NAFLL_DCE			341U

#define TEGRA234_CLK_MPHY_L0_RX_ANA_M		342U

#define TEGRA234_CLK_MPHY_L1_RX_ANA_M		343U

#define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB	344U

#define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV	345U

#define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB		346U

#define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV	347U

#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV	348U

#define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV	349U

#define TEGRA234_CLK_MPHY_L0_TX_SYMB_M		350U

#define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV	351U

#define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV	352U

#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV	353U

#define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV	354U

#define TEGRA234_CLK_MPHY_L0_RX_SYMB_M		355U

#define TEGRA234_CLK_MGBE0_RX_INPUT_M		357U

#define TEGRA234_CLK_MGBE1_RX_INPUT_M		358U

#define TEGRA234_CLK_MGBE2_RX_INPUT_M		359U

#define TEGRA234_CLK_MGBE3_RX_INPUT_M		360U

#define TEGRA234_CLK_MGBE0_RX_PCS_M		361U

#define TEGRA234_CLK_MGBE1_RX_PCS_M		362U

#define TEGRA234_CLK_MGBE2_RX_PCS_M		363U

#define TEGRA234_CLK_MGBE3_RX_PCS_M		364U

#define TEGRA234_CLK_TACH1			365U

#define TEGRA234_CLK_MGBES_APP			366U

#define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF	367U

#define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG		368U

#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT		369U

#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT		370U

#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT		371U

#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT		372U

#define TEGRA234_CLK_MGBE0_RX_PCS		373U

#define TEGRA234_CLK_MGBE0_TX			374U

#define TEGRA234_CLK_MGBE0_TX_PCS		375U

#define TEGRA234_CLK_MGBE0_MAC_DIVIDER		376U

#define TEGRA234_CLK_MGBE0_MAC			377U

#define TEGRA234_CLK_MGBE0_MACSEC		378U

#define TEGRA234_CLK_MGBE0_EEE_PCS		379U

#define TEGRA234_CLK_MGBE0_APP			380U

#define TEGRA234_CLK_MGBE0_PTP_REF		381U

#define TEGRA234_CLK_MGBE1_RX_PCS		382U

#define TEGRA234_CLK_MGBE1_TX			383U

#define TEGRA234_CLK_MGBE1_TX_PCS		384U

#define TEGRA234_CLK_MGBE1_MAC_DIVIDER		385U

#define TEGRA234_CLK_MGBE1_MAC			386U

#define TEGRA234_CLK_MGBE1_MACSEC		387U

#define TEGRA234_CLK_MGBE1_EEE_PCS		388U

#define TEGRA234_CLK_MGBE1_APP			389U

#define TEGRA234_CLK_MGBE1_PTP_REF		390U

#define TEGRA234_CLK_MGBE2_RX_PCS		391U

#define TEGRA234_CLK_MGBE2_TX			392U

#define TEGRA234_CLK_MGBE2_TX_PCS		393U

#define TEGRA234_CLK_MGBE2_MAC_DIVIDER		394U

#define TEGRA234_CLK_MGBE2_MAC			395U

#define TEGRA234_CLK_MGBE2_MACSEC		396U

#define TEGRA234_CLK_MGBE2_EEE_PCS		397U

#define TEGRA234_CLK_MGBE2_APP			398U

#define TEGRA234_CLK_MGBE2_PTP_REF		399U

#define TEGRA234_CLK_MGBE3_RX_PCS		400U

#define TEGRA234_CLK_MGBE3_TX			401U

#define TEGRA234_CLK_MGBE3_TX_PCS		402U

#define TEGRA234_CLK_MGBE3_MAC_DIVIDER		403U

#define TEGRA234_CLK_MGBE3_MAC			404U

#define TEGRA234_CLK_MGBE3_MACSEC		405U

#define TEGRA234_CLK_MGBE3_EEE_PCS		406U

#define TEGRA234_CLK_MGBE3_APP			407U

#define TEGRA234_CLK_MGBE3_PTP_REF		408U

#define TEGRA234_CLK_GBE_RX_BYP_REF		409U

#define TEGRA234_CLK_GBE_PLL0_MGMT		410U

#define TEGRA234_CLK_GBE_PLL1_MGMT		411U

#define TEGRA234_CLK_GBE_PLL2_MGMT		412U

#define TEGRA234_CLK_EQOS_MACSEC_RX		413U

#define TEGRA234_CLK_EQOS_MACSEC_TX		414U

#define TEGRA234_CLK_EQOS_TX_DIVIDER		415U

#define TEGRA234_CLK_NVHS_PLL1_MGMT		416U

#define TEGRA234_CLK_EMCHUB			417U

#define TEGRA234_CLK_I2S7_SYNC_INPUT		418U

#define TEGRA234_CLK_SYNC_I2S7			419U

#define TEGRA234_CLK_I2S7			420U

#define TEGRA234_CLK_I2S7_PAD_M			421U

#define TEGRA234_CLK_I2S8_SYNC_INPUT		422U

#define TEGRA234_CLK_SYNC_I2S8			423U

#define TEGRA234_CLK_I2S8			424U

#define TEGRA234_CLK_I2S8_PAD_M			425U

#define TEGRA234_CLK_NAFLL_GPC0			426U

#define TEGRA234_CLK_NAFLL_GPC1			427U

#define TEGRA234_CLK_NAFLL_GPUSYS		428U

#define TEGRA234_CLK_NAFLL_DSU0			429U 
#define TEGRA234_CLK_NAFLL_CLUSTER0_DSU		429U

#define TEGRA234_CLK_NAFLL_DSU1			430U 
#define TEGRA234_CLK_NAFLL_CLUSTER1_DSU		430U

#define TEGRA234_CLK_NAFLL_DSU2			431U 
#define TEGRA234_CLK_NAFLL_CLUSTER2_DSU		431U

#define TEGRA234_CLK_SCE_CPU			432U

#define TEGRA234_CLK_RCE_CPU			433U

#define TEGRA234_CLK_DCE_CPU			434U

#define TEGRA234_CLK_DSIPLL_VCO			435U

#define TEGRA234_CLK_DSIPLL_CLKOUTPN		436U

#define TEGRA234_CLK_DSIPLL_CLKOUTA		437U

#define TEGRA234_CLK_SPPLL0_VCO			438U

#define TEGRA234_CLK_SPPLL0_CLKOUTPN		439U

#define TEGRA234_CLK_SPPLL0_CLKOUTA		440U

#define TEGRA234_CLK_SPPLL0_CLKOUTB		441U

#define TEGRA234_CLK_SPPLL0_DIV10		442U

#define TEGRA234_CLK_SPPLL0_DIV25		443U

#define TEGRA234_CLK_SPPLL0_DIV27PN		444U

#define TEGRA234_CLK_SPPLL1_VCO			445U

#define TEGRA234_CLK_SPPLL1_CLKOUTPN		446U

#define TEGRA234_CLK_SPPLL1_DIV27PN		447U

#define TEGRA234_CLK_VPLL0_REF			448U

#define TEGRA234_CLK_VPLL0			449U

#define TEGRA234_CLK_VPLL1			450U

#define TEGRA234_CLK_NVDISPLAY_P0_REF		451U

#define TEGRA234_CLK_RG0			452U

#define TEGRA234_CLK_RG1			453U

#define TEGRA234_CLK_DISPPLL			454U

#define TEGRA234_CLK_DISPHUBPLL			455U

#define TEGRA234_CLK_DSI_LP			456U

#define TEGRA234_CLK_AZA_2XBIT			457U

#define TEGRA234_CLK_AZA_BIT			458U

#define TEGRA234_CLK_DSI_CORE			459U

#define TEGRA234_CLK_DSI_PIXEL			460U

#define TEGRA234_CLK_PRE_SOR0			461U

#define TEGRA234_CLK_PRE_SOR1			462U

#define TEGRA234_CLK_DP_LINK_REF		463U

#define TEGRA234_CLK_SOR_LINKA_INPUT		464U

#define TEGRA234_CLK_SOR_LINKA_AFIFO		465U

#define TEGRA234_CLK_SOR_LINKA_AFIFO_M		466U

#define TEGRA234_CLK_RG0_M			467U

#define TEGRA234_CLK_RG1_M			468U

#define TEGRA234_CLK_SOR0_M			469U

#define TEGRA234_CLK_SOR1_M			470U

#define TEGRA234_CLK_PLLHUB			471U

#define TEGRA234_CLK_MCHUB			472U

#define TEGRA234_CLK_EMCSA_MC			473U

#define TEGRA234_CLK_EMCSB_MC			474U

#define TEGRA234_CLK_EMCSC_MC			475U

#define TEGRA234_CLK_EMCSD_MC			476U



#endif
