// SPDX-License-Identifier: GPL-2.0-only

#ifndef _LINUX_PSE_CONTROLLER_H
#define _LINUX_PSE_CONTROLLER_H

#include <linux/list.h>
#include <linux/netlink.h>
#include <linux/kfifo.h>
#include <uapi/linux/ethtool.h>
#include <uapi/linux/ethtool_netlink_generated.h>
#include <linux/regulator/driver.h>


#define MAX_PI_CURRENT 1920000

#define MAX_PI_PW 99900

struct net_device;
struct phy_device;
struct pse_controller_dev;
struct netlink_ext_ack;


struct ethtool_c33_pse_ext_state_info {
	enum ethtool_c33_pse_ext_state c33_pse_ext_state;
	union {
		enum ethtool_c33_pse_ext_substate_error_condition error_condition;
		enum ethtool_c33_pse_ext_substate_mr_pse_enable mr_pse_enable;
		enum ethtool_c33_pse_ext_substate_option_detect_ted option_detect_ted;
		enum ethtool_c33_pse_ext_substate_option_vport_lim option_vport_lim;
		enum ethtool_c33_pse_ext_substate_ovld_detected ovld_detected;
		enum ethtool_c33_pse_ext_substate_power_not_available power_not_available;
		enum ethtool_c33_pse_ext_substate_short_detected short_detected;
		u32 __c33_pse_ext_substate;
	};
};

struct ethtool_c33_pse_pw_limit_range {
	u32 min;
	u32 max;
};


struct pse_irq_desc {
	const char *name;
	int (*map_event)(int irq, struct pse_controller_dev *pcdev,
			 unsigned long *notifs,
			 unsigned long *notifs_mask);
};


struct pse_control_config {
	enum ethtool_podl_pse_admin_state podl_admin_control;
	enum ethtool_c33_pse_admin_state c33_admin_control;
};


struct pse_admin_state {
	enum ethtool_podl_pse_admin_state podl_admin_state;
	enum ethtool_c33_pse_admin_state c33_admin_state;
};


struct pse_pw_status {
	enum ethtool_podl_pse_pw_d_status podl_pw_status;
	enum ethtool_c33_pse_pw_d_status c33_pw_status;
};


struct pse_ext_state_info {
	struct ethtool_c33_pse_ext_state_info c33_ext_state_info;
};


struct pse_pw_limit_ranges {
	struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
};


struct ethtool_pse_control_status {
	u32 pw_d_id;
	enum ethtool_podl_pse_admin_state podl_admin_state;
	enum ethtool_podl_pse_pw_d_status podl_pw_status;
	enum ethtool_c33_pse_admin_state c33_admin_state;
	enum ethtool_c33_pse_pw_d_status c33_pw_status;
	u32 c33_pw_class;
	u32 c33_actual_pw;
	struct ethtool_c33_pse_ext_state_info c33_ext_state_info;
	u32 c33_avail_pw_limit;
	struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
	u32 c33_pw_limit_nb_ranges;
	u32 prio_max;
	u32 prio;
};


struct pse_controller_ops {
	int (*setup_pi_matrix)(struct pse_controller_dev *pcdev);
	int (*pi_get_admin_state)(struct pse_controller_dev *pcdev, int id,
				  struct pse_admin_state *admin_state);
	int (*pi_get_pw_status)(struct pse_controller_dev *pcdev, int id,
				struct pse_pw_status *pw_status);
	int (*pi_get_ext_state)(struct pse_controller_dev *pcdev, int id,
				struct pse_ext_state_info *ext_state_info);
	int (*pi_get_pw_class)(struct pse_controller_dev *pcdev, int id);
	int (*pi_get_actual_pw)(struct pse_controller_dev *pcdev, int id);
	int (*pi_enable)(struct pse_controller_dev *pcdev, int id);
	int (*pi_disable)(struct pse_controller_dev *pcdev, int id);
	int (*pi_get_voltage)(struct pse_controller_dev *pcdev, int id);
	int (*pi_get_pw_limit)(struct pse_controller_dev *pcdev,
			       int id);
	int (*pi_set_pw_limit)(struct pse_controller_dev *pcdev,
			       int id, int max_mW);
	int (*pi_get_pw_limit_ranges)(struct pse_controller_dev *pcdev, int id,
				      struct pse_pw_limit_ranges *pw_limit_ranges);
	int (*pi_get_prio)(struct pse_controller_dev *pcdev, int id);
	int (*pi_set_prio)(struct pse_controller_dev *pcdev, int id,
			   unsigned int prio);
	int (*pi_get_pw_req)(struct pse_controller_dev *pcdev, int id);
};

struct module;
struct device_node;
struct of_phandle_args;
struct pse_control;
struct ethtool_pse_control_status;


enum pse_pi_pairset_pinout {
	ALTERNATIVE_A,
	ALTERNATIVE_B,
};


struct pse_pi_pairset {
	enum pse_pi_pairset_pinout pinout;
	struct device_node *np;
};


struct pse_pi {
	struct pse_pi_pairset pairset[2];
	struct device_node *np;
	struct regulator_dev *rdev;
	bool admin_state_enabled;
	struct pse_power_domain *pw_d;
	int prio;
	bool isr_pd_detected;
	int pw_allocated_mW;
};


struct pse_ntf {
	int id;
	unsigned long notifs;
};


struct pse_controller_dev {
	const struct pse_controller_ops *ops;
	struct module *owner;
	struct list_head list;
	struct list_head pse_control_head;
	struct device *dev;
	int of_pse_n_cells;
	unsigned int nr_lines;
	struct mutex lock;
	enum ethtool_pse_types types;
	struct pse_pi *pi;
	bool no_of_pse_pi;
	int irq;
	unsigned int pis_prio_max;
	u32 supp_budget_eval_strategies;
	struct work_struct ntf_work;
	DECLARE_KFIFO_PTR(ntf_fifo, struct pse_ntf);
	spinlock_t ntf_fifo_lock; 
};



enum pse_budget_eval_strategies {
	PSE_BUDGET_EVAL_STRAT_DISABLED	= 1 << 0,
	PSE_BUDGET_EVAL_STRAT_STATIC	= 1 << 1,
	PSE_BUDGET_EVAL_STRAT_DYNAMIC	= 1 << 2,
};

#if IS_ENABLED(CONFIG_PSE_CONTROLLER)
int pse_controller_register(struct pse_controller_dev *pcdev);
void pse_controller_unregister(struct pse_controller_dev *pcdev);
struct device;
int devm_pse_controller_register(struct device *dev,
				 struct pse_controller_dev *pcdev);
int devm_pse_irq_helper(struct pse_controller_dev *pcdev, int irq,
			int irq_flags, const struct pse_irq_desc *d);

struct pse_control *of_pse_control_get(struct device_node *node,
				       struct phy_device *phydev);
void pse_control_put(struct pse_control *psec);

int pse_ethtool_get_status(struct pse_control *psec,
			   struct netlink_ext_ack *extack,
			   struct ethtool_pse_control_status *status);
int pse_ethtool_set_config(struct pse_control *psec,
			   struct netlink_ext_ack *extack,
			   const struct pse_control_config *config);
int pse_ethtool_set_pw_limit(struct pse_control *psec,
			     struct netlink_ext_ack *extack,
			     const unsigned int pw_limit);
int pse_ethtool_set_prio(struct pse_control *psec,
			 struct netlink_ext_ack *extack,
			 unsigned int prio);

bool pse_has_podl(struct pse_control *psec);
bool pse_has_c33(struct pse_control *psec);

#else

static inline struct pse_control *of_pse_control_get(struct device_node *node,
						     struct phy_device *phydev)
{
	return ERR_PTR(-ENOENT);
}

static inline void pse_control_put(struct pse_control *psec)
{
}

static inline int pse_ethtool_get_status(struct pse_control *psec,
					 struct netlink_ext_ack *extack,
					 struct ethtool_pse_control_status *status)
{
	return -EOPNOTSUPP;
}

static inline int pse_ethtool_set_config(struct pse_control *psec,
					 struct netlink_ext_ack *extack,
					 const struct pse_control_config *config)
{
	return -EOPNOTSUPP;
}

static inline int pse_ethtool_set_pw_limit(struct pse_control *psec,
					   struct netlink_ext_ack *extack,
					   const unsigned int pw_limit)
{
	return -EOPNOTSUPP;
}

static inline int pse_ethtool_set_prio(struct pse_control *psec,
				       struct netlink_ext_ack *extack,
				       unsigned int prio)
{
	return -EOPNOTSUPP;
}

static inline bool pse_has_podl(struct pse_control *psec)
{
	return false;
}

static inline bool pse_has_c33(struct pse_control *psec)
{
	return false;
}

#endif

#endif
