/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SPI_SH_MSIOF_H__
#define __SPI_SH_MSIOF_H__

#include <linux/bitfield.h>
#include <linux/bits.h>

#define SITMDR1	0x00	
#define SITMDR2	0x04	
#define SITMDR3	0x08	
#define SIRMDR1	0x10	
#define SIRMDR2	0x14	
#define SIRMDR3	0x18	
#define SITSCR	0x20	
#define SIRSCR	0x22	
#define SICTR	0x28	
#define SIFCTR	0x30	
#define SISTR	0x40	
#define SIIER	0x44	
#define SITDR1	0x48	
#define SITDR2	0x4c	
#define SITFDR	0x50	
#define SIRDR1	0x58	
#define SIRDR2	0x5c	
#define SIRFDR	0x60	


#define SIMDR1_TRMD		BIT(31)		
#define SIMDR1_SYNCMD		GENMASK(29, 28)	
#define SIMDR1_SYNCMD_PULSE	0U		
#define SIMDR1_SYNCMD_SPI	2U		
#define SIMDR1_SYNCMD_LR	3U		
#define SIMDR1_SYNCAC		BIT(25)		
#define SIMDR1_BITLSB		BIT(24)		
#define SIMDR1_DTDL		GENMASK(22, 20)	
#define SIMDR1_SYNCDL		GENMASK(18, 16)	
#define SIMDR1_FLD		GENMASK(3, 2)	
#define SIMDR1_XXSTP		BIT(0)		

#define SITMDR1_PCON		BIT(30)		
#define SITMDR1_SYNCCH		GENMASK(27, 26)	
						


#define SIMDR2_GRP		GENMASK(31, 30)	
#define SIMDR2_BITLEN1		GENMASK(28, 24)	
#define SIMDR2_WDLEN1		GENMASK(23, 16)	
#define SIMDR2_GRPMASK		GENMASK(3, 0)	


#define SIMDR3_BITLEN2		GENMASK(28, 24)	
#define SIMDR3_WDLEN2		GENMASK(23, 16)	


#define SISCR_BRPS		GENMASK(12, 8)	
#define SISCR_BRDV		GENMASK(2, 0)	


#define SICTR_TSCKIZ		GENMASK(31, 30)	
#define SICTR_TSCKIZ_SCK	BIT(31)		
#define SICTR_TSCKIZ_POL	BIT(30)		
#define SICTR_RSCKIZ		GENMASK(29, 28) 
#define SICTR_RSCKIZ_SCK	BIT(29)		
#define SICTR_RSCKIZ_POL	BIT(28)		
#define SICTR_TEDG		BIT(27)		
#define SICTR_REDG		BIT(26)		
#define SICTR_TXDIZ		GENMASK(23, 22)	
#define SICTR_TXDIZ_LOW		0U		
#define SICTR_TXDIZ_HIGH	1U		
#define SICTR_TXDIZ_HIZ		2U		
#define SICTR_TSCKE		BIT(15)		
#define SICTR_TFSE		BIT(14)		
#define SICTR_TXE		BIT(9)		
#define SICTR_RXE		BIT(8)		
#define SICTR_TXRST		BIT(1)		
#define SICTR_RXRST		BIT(0)		


#define SIFCTR_TFWM		GENMASK(31, 29)	
#define SIFCTR_TFWM_64		0U		
#define SIFCTR_TFWM_32		1U		
#define SIFCTR_TFWM_24		2U		
#define SIFCTR_TFWM_16		3U		
#define SIFCTR_TFWM_12		4U		
#define SIFCTR_TFWM_8		5U		
#define SIFCTR_TFWM_4		6U		
#define SIFCTR_TFWM_1		7U		
#define SIFCTR_TFUA		GENMASK(28, 20) 
#define SIFCTR_RFWM		GENMASK(15, 13)	
#define SIFCTR_RFWM_1		0U		
#define SIFCTR_RFWM_4		1U		
#define SIFCTR_RFWM_8		2U		
#define SIFCTR_RFWM_16		3U		
#define SIFCTR_RFWM_32		4U		
#define SIFCTR_RFWM_64		5U		
#define SIFCTR_RFWM_128		6U		
#define SIFCTR_RFWM_256		7U		
#define SIFCTR_RFUA		GENMASK(12, 4)	


#define SISTR_TFEMP		BIT(29) 
#define SISTR_TDREQ		BIT(28) 
#define SISTR_TEOF		BIT(23) 
#define SISTR_TFSERR		BIT(21) 
#define SISTR_TFOVF		BIT(20) 
#define SISTR_TFUDF		BIT(19) 
#define SISTR_RFFUL		BIT(13) 
#define SISTR_RDREQ		BIT(12) 
#define SISTR_REOF		BIT(7)  
#define SISTR_RFSERR		BIT(5)  
#define SISTR_RFUDF		BIT(4)  
#define SISTR_RFOVF		BIT(3)  


#define SIIER_TDMAE		BIT(31) 
#define SIIER_TFEMPE		BIT(29) 
#define SIIER_TDREQE		BIT(28) 
#define SIIER_TEOFE		BIT(23) 
#define SIIER_TFSERRE		BIT(21) 
#define SIIER_TFOVFE		BIT(20) 
#define SIIER_TFUDFE		BIT(19) 
#define SIIER_RDMAE		BIT(15) 
#define SIIER_RFFULE		BIT(13) 
#define SIIER_RDREQE		BIT(12) 
#define SIIER_REOFE		BIT(7)  
#define SIIER_RFSERRE		BIT(5)  
#define SIIER_RFUDFE		BIT(4)  
#define SIIER_RFOVFE		BIT(3)  

enum {
	MSIOF_SPI_HOST,
	MSIOF_SPI_TARGET,
};

struct sh_msiof_spi_info {
	int tx_fifo_override;
	int rx_fifo_override;
	u16 num_chipselect;
	int mode;
	unsigned int dma_tx_id;
	unsigned int dma_rx_id;
	u32 dtdl;
	u32 syncdl;
};

#endif 
